The present invention relates to a method of laying out a semiconductor integrated circuit (SIC) with the aid of a computer. It more particularly pertains to an SIC layout technique for placing and interconnecting digital logic circuits or like components of a semiconductor integrated circuit.
In the design of large-scale integrated circuits (LSIs), it is required to meet limitations on the propagation delay time taken for a signal to propagate from one circuit to another and it is also very important to provide a semiconductor integrated circuit of minimum layout area, for the aspects of performance and costs. As the circuit scale of SIC increases the operating frequency thereof likewise increases. This results in an increase in the severity of a delay limitation imposed on the propagation delay time in a design phase. In an initial layout of a semiconductor integrated circuit, it is very important to modify the initial layout by reducing the signal propagation delay time of a wire involving a violation of the delay limitation, in order to cancel the delay limitation violation.
A conventional technique is discusses. When a layout is completed, the capacitance and resistance values of laid-out wires are exactly grasped and, based on the values, the signal propagation delay time of each wire is calculated. When a violation of the delay limitation is found, i.e., when any wire is found to have a signal propagation delay time in excess of a predetermined delay time, there are two ways of achieving a reduction of the signal propagation delay time. In the first way, a transistor in charge of driving a wire involving a violation of the delay limitation is replaced by another transistor having greater driving performance. In the second way, a violational wire is rerouted in order to reduce the length thereof.
The world of SIC enters now the deep-submicron age. As the cross-sectional area of wires is reduced, the resistance thereof increases. Additionally, the reduction of wire width and the reduction of wire spacing result in an increase in interwire capacitance (the capacitance between two adjacent wires), which therefore increases the total wire capacitance. Such increases in the total wire capacitance and in the wire resistance result in a longer signal propagation delay time. In regard to the signal propagation delay, wire delay becomes dominant in comparison with circuit component delay.
Accordingly, the foregoing conventional technique of making a change in the transistor driving performance may not be a very effective way of canceling violations of the delay limitation when wire delay becomes dominant.
For the case of rerouting a wire involving a violation of the delay limitation, it is also necessary to reroute its neighboring wires even when they are conformable to the delay limitation. Further, such rerouting may produce new violations of the delay limitation. Accordingly, the number of times such rerouting is carried out is increased. This is very time consuming. Much time is required to complete a design, and there is the possibility that repetition of the processing of rerouting will not make every wire free from a violation of the delay limitation.